Device and method for the synchronization of clock signals...

Details Device and method for the synchronization of clock signals... Device and method for the synchronization of clock signals...

2006-08-02

2008-08-19

Richards, N. Drew (Department: 2816)

Miscellaneous active electrical nonlinear devices, circuits, and

Signal converting, shaping, or generating

Synchronizing

C327S149000, C327S175000, C365S233100

Reexamination Certificate

active

07414445

ABSTRACT:
A device for synchronizing an input clock signal with an output clock signal is disclosed. One embodiment includes includes a bistable trigger circuit for controlling the edges of a clock signal fed to a first delay, a second phase comparator for determining the phase between the first clock signal delayed by the first delay and the input clock signal, and a second controller for controlling the delay of the first clock signal in correspondence with the phase determined by the second phase comparator.

REFERENCES:
patent: 6127866 (2000-10-01), Chu et al.
patent: 6486716 (2002-11-01), Minami et al.
patent: 6642760 (2003-11-01), Alon et al.
patent: 7199625 (2007-04-01), Chung
patent: 2003/0067015 (2003-04-01), Drexler
patent: 0964517 (1999-12-01), None
“Digital delay locked loop with open-loop digital duty cycle corrector for 1.2Gb/s/pin double data rate SDRAM”, Chunseok Jeong, Changsik Yoo, Jae-Jin Lee, and Joongsik Kih, IEEE, 2004.

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