Semiconductor memory device

Static information storage and retrieval – Format or disposition of elements

Reexamination Certificate

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C365S230010, C365S230030

Reexamination Certificate

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07414874

ABSTRACT:
Disclosed is a semiconductor memory device comprising a memory cell array block, and a circuit region arranged with the memory cell array block along a first direction. The circuit region comprises a first region and a second region arranged with the first region along the first direction. The first region is provided with a first circuit and a second circuit which are aligned in a second direction perpendicular to the first direction. The second region is provided with a plurality of third circuits which are aligned in the second direction.

REFERENCES:
patent: 6314042 (2001-11-01), Tomishima et al.
patent: 6418067 (2002-07-01), Watanabe et al.
patent: 6646946 (2003-11-01), Tomishima et al.
patent: 6781915 (2004-08-01), Arimoto et al.
patent: 7110282 (2006-09-01), Kono et al.
patent: 2004/0085839 (2004-05-01), Takemura et al.
patent: 2005/0068838 (2005-03-01), Kono et al.
patent: 2000-243085 (2000-09-01), None

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