Semiconductor memory device and driving method of the same

Static information storage and retrieval – Floating gate – Particular biasing

Reexamination Certificate

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C365S185050, C365S185180

Reexamination Certificate

active

07433242

ABSTRACT:
A semiconductor memory device includes a semiconductor substrate including a semiconductor layer on a first insulation film; a memory cell including a source and a drain formed in the semiconductor layer, and a floating body region provided between the source and the drain, the memory cell storing data according to an amount of charges accumulated in the floating body region; a second insulation film provided on the floating body region of the memory cell; a word line provided on the second insulation film; a bit line connected to the drain; a source line connected to the source; and a plate electrode electrically insulated from the floating body region by the first insulation film, wherein in at least a part of a period for writing data to the memory cell, a potential of the plate electrode is changed to reduce an absolute value of a threshold voltage of the memory cell.

REFERENCES:
patent: 6538916 (2003-03-01), Ohsawa
patent: 6617651 (2003-09-01), Ohsawa
patent: 6687152 (2004-02-01), Ohsawa
patent: 6946712 (2005-09-01), Asao
patent: 6949768 (2005-09-01), Anderson et al.
patent: 7016226 (2006-03-01), Shibata et al.
patent: 7042052 (2006-05-01), Bhattacharyya
patent: 2005/0128787 (2005-06-01), Mouli
patent: 2007/0007574 (2007-01-01), Ohsawa
patent: 2007/0064482 (2007-03-01), Takeuchi
U.S. Appl. No. 12/031,111, filed Feb. 14, 2008, Ohsawa.

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