Integrated device including connections on a separate wafer

Details Integrated device including connections on a separate wafer Integrated device including connections on a separate wafer

2004-12-07

2008-10-07

Vu, Hung (Department: 2811)

Active solid-state devices (e.g., transistors, solid-state diode

Housing or package

Multiple housings

C257S685000, C257S777000

Reexamination Certificate

active

07432587

ABSTRACT:
An integrated semiconductor device includes semiconductor regions and isolation regions in a first wafer of semiconductor material, and, on a second wafer of semiconductor material, interconnection structures. Plug elements provide electrical and mechanical coupling between the first and second wafers. Each plug element includes a first region coupled to the first wafer and a second region formed of a selected metal bonded with the semiconductor regions of the first wafer, forming a metal silicide.

REFERENCES:
patent: 3254389 (1966-06-01), Andres et al.
patent: 5406701 (1995-04-01), Pepe et al.
patent: 5627106 (1997-05-01), Hsu
patent: 5654226 (1997-08-01), Temple et al.
patent: 5756395 (1998-05-01), Rostoker et al.
patent: 5801083 (1998-09-01), Yu et al.
patent: 5858814 (1999-01-01), Goossen et al.
patent: 6479320 (2002-11-01), Gooch
patent: 0908951 (1999-04-01), None
patent: 0 993 034 (2000-04-01), None
Ismail, M.S. et al., “Platinum Silicide Fusion Bonding,”Electronic Letters, 27(13):1153-1155, Jun. 20, 1991.
Fukuroda, A. et al., “Si Wafer Bonding with Ta Silicide Formation,”Japanese Journal of Applied Physics, 30(10A):L1693-L1695, Oct. 1991.
Chaput, M., “Aligning Wafer Stacks with Machine Vision,”Global Semiconductor, Imaging Technology Incorporated.
Ismail, M.S. et al., “Platinum Silicide Fusion Bonding,”Electronic Letters, 27(13):1153-1155, Jun. 20, 1991.
Fukuroda, A. et al., “Si Wafer Bonding with Ta Silicide Formation,”Japanese Journal of Applied Physics, 30(10A):L1693-L1695, Oct. 1991.

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