Process for fabricating chip package structure

Details Process for fabricating chip package structure Process for fabricating chip package structure

2005-04-27

2008-08-05

Gurley, Lynne A. (Department: 2811)

Semiconductor device manufacturing: process

Packaging or treatment of packaged semiconductor

Assembly of plural semiconductive substrates each possessing...

C257S778000, C257S737000, C257S780000

Reexamination Certificate

active

07407833

ABSTRACT:
A chip package structure comprising a carrier, a chip and an underfill layer is disclosed. The carrier has a plurality of bumps disposed thereon. The chip has an active surface. The chip is flip-chip bonded and electrically connected to the carrier through the bumps such that the active surface of the chip faces the carrier. The underfill layer is disposed on the carrier between the chip and the carrier such that a gap is maintained between the underfill layer and the chip.

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patent: 2001-298145 (2001-10-01), None
patent: 2001-298148 (2001-10-01), None

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