Semiconductor device manufacturing: process – Packaging or treatment of packaged semiconductor
Reexamination Certificate
2006-08-18
2008-08-05
Huynh, Andy (Department: 2818)
Semiconductor device manufacturing: process
Packaging or treatment of packaged semiconductor
C438S112000, C438S124000, C438S127000, C257SE21504, C257SE23125, C156S500000, C249S095000, C425S116000
Reexamination Certificate
active
07407832
ABSTRACT:
A die for encapsulating an IC structural body having bonding wires with a molten resin is provided with at least one first half having an ejector-pin-through-hole and at least one second half coupled together to form a cavity therebetween. An ejector pin having a mirror-finished surface at a tip end thereof is inserted into the ejector-pin-through-hole and positioned at a position where a surface of the tip end of the ejector pin coincides with an intermediate surface height of a satin-finished surface formed on an upper inner wall of the cavity of the first half. The IC structural body is then encapsulated with a molten resin, and the mirror-finished surface of the ejector pin and the satin-finished surface of the upper inner wall surface of the cavity are stamped on the semiconductor package in substantially the same plane.
REFERENCES:
patent: 5663104 (1997-09-01), Fukuyama
patent: 5817208 (1998-10-01), Nose et al.
patent: 5874324 (1999-02-01), Osada
patent: 6276913 (2001-08-01), Mitsui et al.
patent: 6430034 (2002-08-01), Sano et al.
patent: 11-087565 (1999-03-01), None
patent: 2001-160604 (2001-06-01), None
The Nikkan Kogyo Shinbun, Ltd., 1989, “Handbook of Die and Mold Technology”, Japanese Society of Die and Mould Technology, ed.
Huynh Andy
Oki Electric Industry Co. Ltd.
Volentine & Whitt P.L.L.C.
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