Method and apparatus for configuring the operating speed of...

Static information storage and retrieval – Addressing – Sync/clocking

Reexamination Certificate

Rate now

  [ 0.00 ] – not rated yet Voters 0   Comments 0

Details

C365S233140, C365S196000, C365S195000, C365S194000, C365S189050, C326S038000, C326S040000, C326S046000

Reexamination Certificate

active

07417918

ABSTRACT:
Method and apparatus for configuring a programmable logic device to operate at a plurality of clock frequencies comprising configurable programmable self-timed delay circuits and associated configuration software. The configurable IC clock frequencies increase device performance and manufacturing yield.

REFERENCES:
patent: 5386388 (1995-01-01), Atwood et al.
patent: 5964884 (1999-10-01), Partovi et al.
patent: 6201757 (2001-03-01), Ward et al.
patent: 6212117 (2001-04-01), Shin et al.
patent: 6301176 (2001-10-01), Brown
patent: 6438057 (2002-08-01), Ruckerbauer
patent: 6785184 (2004-08-01), Nguyen et al.
patent: 7132851 (2006-11-01), Young
patent: 7164289 (2007-01-01), Choe et al.
patent: 7187200 (2007-03-01), Young

LandOfFree

Say what you really think

Search LandOfFree.com for the USA inventors and patents. Rate them and share your experience with other people.

Rating

Method and apparatus for configuring the operating speed of... does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Method and apparatus for configuring the operating speed of..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Method and apparatus for configuring the operating speed of... will most certainly appreciate the feedback.

Rate now

     

Profile ID: LFUS-PAI-O-4001023

  Search
All data on this website is collected from public sources. Our data reflects the most accurate information available at the time of publication.