Electrical computers: arithmetic processing and calculating – Electrical digital calculating computer – Particular function performed
Reexamination Certificate
2005-03-14
2008-10-14
Malzahn, David H (Department: 2193)
Electrical computers: arithmetic processing and calculating
Electrical digital calculating computer
Particular function performed
Reexamination Certificate
active
07437400
ABSTRACT:
A data processing apparatus and method are provided for adding n-bit significands of first and second floating point operands to produce an n-bit result. The data processing apparatus comprises determination logic for determining which of the first and second floating point operands is the larger operand. First adder logic is used, if predetermined criteria exists, to perform an addition of the n-bit significands of the first and second floating point operands to produce the sum value, whilst second adder logic is used, if the predetermined criteria does not exist, to perform that addition. Result logic can then derive the n-bit result from either an output of the first adder logic or an output of the second adder logic. If the addition is a like-signed addition, the predetermined criteria is determined to exist for a set of situations where the sum value produced by the first adder logic will require an effective 1-bit right shift to normalise the sum value, whereas if the addition is an unlike-signed addition, the predetermined criteria is determined to exist for a set of situations where the sum value produced by the first adder logic will require at least an effective 1-bit left shift to normalise the sum value.
REFERENCES:
patent: 5677861 (1997-10-01), Inoue et al.
patent: 5808926 (1998-09-01), Gorshtein et al.
patent: 6085212 (2000-07-01), Oberman
patent: 6088715 (2000-07-01), Oberman
patent: 6094668 (2000-07-01), Oberman
patent: 6397239 (2002-05-01), Oberman et al.
patent: 2006/0136543 (2006-06-01), Lutz et al.
A. Naini et al., “1-GHz HAL SPARC64® Dual Floating Point Unit with RAS Features”, Proceedings of the 15thIEEE Symposium on Computer Arithmetic (ARITH'01).
Hinds Christopher Neal
Lutz David Raymond
ARM Limited
Malzahn David H
Nixon & Vanderhye P.C.
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