Oscillators – Automatic frequency stabilization using a phase or frequency... – Tuning compensation
Reexamination Certificate
2006-09-28
2008-10-21
Chang, Joseph (Department: 2817)
Oscillators
Automatic frequency stabilization using a phase or frequency...
Tuning compensation
C331S011000
Reexamination Certificate
active
07439816
ABSTRACT:
Phase-locked loop fast lock circuit and method are described. The apparatus including a voltage controlled oscillator, a control loop filter having a capacitor and at least one resistor, and first and second control elements coupled with the control loop filter. The first control element may include a charge pump coupled to a node between the resistor and the capacitor of the control loop filter, and a frequency detector coupled to the charge pump.
REFERENCES:
patent: 2001/0015677 (2001-08-01), Choi
Y. Fouzar, M. Sawan, Y. Savaria, “Very short locking time PLL based on controlled gain technique”,ICECS 2000—IEEE International Conference on Electronics, Circuits and Systems, Dec. 17-20, 2000, vol. 1, pp. 252-255.
Y. Fouzar, M. Sawan, Y. Savaria, “A New Fully Integrated CMOS Phase-Locked Loop with Low Jitter and Fast Lock Time”,ISCAS 2000—IEEE International Symposium on Circuits and Systems, May 28-31, 2000, vol. 2, pp. 253-256.
“Phase-locked loop” http://en.wikipedia.org/wiki/Phase-locked loop, May 29, 2006, 10 pages.
1.8V, 500-MHz, 10-Output JEDEC-Compliant Zero Delay Buffer, Cypress Advance Information, Feb. 12, 2004, 9 pages.
Blakely , Sokoloff, Taylor & Zafman LLP
Chang Joseph
Cypress Semiconductor Corporation
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