Analog digital converter (ADC) having improved stability and...

Coded data generation or conversion – Analog to or from digital conversion – Differential encoder and/or decoder

Reexamination Certificate

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Details

C341S118000, C341S120000, C341S155000

Reexamination Certificate

active

07436336

ABSTRACT:
A sigma delta (ΣΔ) analog to digital converter (ADC) that compensates for the adverse effects associated with the time delay introduced by delay circuitry of the feedback loop. This ΣΔ ADC includes a first summing stage, first integrator, second summing stage, second integrator, quantizer, and feedback loop. The second integrator has associated with it a feed forward pass operable to reduce negative effects of delay circuitry within the feed back loop. Feedback loop includes delay circuitry and a number of digital to analog converters. The feed forward path that reduces the effects of the delay includes a resistance within the second or additional integrator. This allows the adverse effects of the time delays associated, which may lead to circuit instability or meta-stability, to be reduced or eliminated.

REFERENCES:
patent: 6404368 (2002-06-01), Yamaguchi
patent: 6697000 (2004-02-01), LeReverend et al.
patent: 6940436 (2005-09-01), Hezar et al.
patent: 7123177 (2006-10-01), Cheng et al.
patent: 2003/0169193 (2003-09-01), LeReverend et al.
patent: 2006/0164270 (2006-07-01), Miller et al.
patent: 2007/0139240 (2007-06-01), Mitteregger et al.
patent: 2007/0171109 (2007-07-01), Mitteregger
patent: 2007/0188362 (2007-08-01), Doerrer et al.

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