Methods to achieve precision alignment for wafer scale packages

Details Methods to achieve precision alignment for wafer scale packages Methods to achieve precision alignment for wafer scale packages

2004-11-22

2008-10-28

Kebede, Brook (Department: 2823)

Semiconductor device manufacturing: process

Packaging or treatment of packaged semiconductor

Assembly of plural semiconductive substrates each possessing...

C438S125000

Reexamination Certificate

active

07442579

ABSTRACT:
Methods for manufacturing an integrated wafer scale package that reduces a potential misalignment between a chip and a pocket of a carrier substrate. According to one aspect of the present invention, a method for manufacturing a semiconductor device includes a photoresist layer disposed on a carrier substrate, a chip placed onto a surface of the photoresist layer. The photoresist layer is patterned using the chip as a mask. The chip is removed from the photoresist layer after the patterning step. A pocket is formed in the carrier substrate, and the chip that was removed is placed into the pocket formed in the carrier substrate.

REFERENCES:
patent: 7005319 (2006-02-01), Chen et al.
patent: 2006/0110851 (2006-05-01), Burrell et al.

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