Superscalar processor with direct result bypass between executio

Details Superscalar processor with direct result bypass between executio Superscalar processor with direct result bypass between executio

1994-04-07

1997-06-03

Ellis, Richard L.

G06F 938

Patent

active

056363532

ABSTRACT:
The disclosed is an improved superscalar processor for reducing the time required for execution of an instruction. The superscalar processor includes an instruction fetching stage, an instruction decoding stage, and function units each having a pipeline structure. A function unit includes an execution stage, a memory access stage, and a write back stage. Function units are connected through a newly provided bypass line. Data obtained by preceding execution in the other function unit (the other pipeline) is applied through the bypass line to a function unit (pipeline) for executing a later instruction. Executed data is transmitted between pipelines without through a register file, so that it becomes unnecessary for the pipeline requesting the executed data to wait for termination of execution of the other pipeline. As a result, time required for execution of an instruction is reduced.

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