Method and apparatus for utilizing condensed instructions

Details Method and apparatus for utilizing condensed instructions Method and apparatus for utilizing condensed instructions

1994-12-16

1997-06-03

Harrell, Robert B.

G06F 930

Patent

active

056363524

ABSTRACT:
A method and apparatus for executing a condensed instruction stream by a processor including receiving an instruction including an instruction identifier and multiple of instruction synonyms within the instruction, generating at least one full width instruction for each instruction synonym, and executing by the processor the generated full width instructions.

REFERENCES:
patent: 4773039 (1988-09-01), Zamora
patent: 4835679 (1989-05-01), Kida et al.
patent: 5019967 (1991-05-01), Wheeler et al.
patent: 5440701 (1995-08-01), Matsuzaki et al.
patent: 5463746 (1995-10-01), Brodnax et al.
IBM TDB "Opcode Remap and Compression in Hard-Wired RISC Microprocessor", vol. 32, No. 10A, Nov. 1990, p. 349.

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