Semiconductor device including MOS transistors having...

Details Semiconductor device including MOS transistors having... Semiconductor device including MOS transistors having...

2006-05-19

2008-09-09

Phung, Anh (Department: 2824)

Static information storage and retrieval

Floating gate

Particular biasing

C365S230060

Reexamination Certificate

active

07423910

ABSTRACT:
A semiconductor memory device includes memory cells, a memory cell array, word lines, a row decoder, and first and second MOS transistors. The memory cell has a floating gate and a control gate. The word line connects commonly the control gates. The row decoder decodes a row address signal. The first MOS transistor transfers a first voltage to the word line unselected by the row decoder. The first MOS transistor has a drain connected to the word line and a source to which the first voltage is applied. A back gate bias for the first MOS transistor is controlled independently of a potential at the source of the first MOS transistor. The second MOS transistor transfers a second voltage to the word line selected by the row decoder. The second MOS transistor has a drain connected to the word line and a source to which the second potential is applied.

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