Timer based stall avoidance mechanism for high speed...

Details Timer based stall avoidance mechanism for high speed... Timer based stall avoidance mechanism for high speed...

2002-12-09

2008-10-14

Milord, Marceau (Department: 2618)

Multiplex communications

Communication over free space

Having a plurality of contiguous regions served by...

C370S236000, C370S394000, C370S349000, C370S389000, C370S235000, C370S392000, C370S252000, C709S236000, C709S221000, C709S235000, C714S748000, C714S752000

Reexamination Certificate

active

07436795

ABSTRACT:
This invention uses timers at the transmitter to track its sending data blocks to improve the timer-based stall avoidance mechanism of the prior art. Moreover, the invention uses a multi-timer mechanism to manage reordering buffers at the receiver. The multi-timer mechanism provides the receiver with one timer per reorder buffer, or uses one timer per missing data block, or uses one timer per missing data block but a gap of consecutive TSN missing data blocks can share one timer. The multi-timer mechanism can effectively track the missing blocks and monitor the reorder delivery process for all reordering buffers.

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3rdGeneration Partnership Project, Technical Specification Group High Speed Downlink (HSDPA) Overall description, Stage 2 (Release 5).
3rdGeneration Partnership Project; TSG-RAM WG2 meeting #24 Oct. 22-26, 2001 HARQ Stall Avoidance (R2-012330).

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