Static information storage and retrieval – Floating gate – Particular biasing
Reexamination Certificate
2006-12-29
2008-10-07
Lam, David (Department: 2827)
Static information storage and retrieval
Floating gate
Particular biasing
C365S185170, C365S185180, C365S203000
Reexamination Certificate
active
07433241
ABSTRACT:
Unselected groups of non-volatile storage elements are boosted during programming to reduce or eliminate program disturb for targeted, but unselected memory cells connected to a selected word line. Prior to applying a program voltage to the selected word line and boosting the unselected groups, the unselected groups are pre-charged to further reduce or eliminate program disturb by providing a larger boosted potential for the unselected groups. During pre-charging, one or more pre-charge enable signals are provided at higher voltages for certain memory cells that may have undergone partial programming.
REFERENCES:
patent: 5043940 (1991-08-01), Harari
patent: 5172338 (1992-12-01), Mehrotra
patent: 5570315 (1996-10-01), Tanaka
patent: 5621684 (1997-04-01), Jung
patent: 5621689 (1997-04-01), Sakakibara et al.
patent: 5677873 (1997-10-01), Choi
patent: 5715194 (1998-02-01), Hu
patent: 5774397 (1998-06-01), Endoh
patent: 5818757 (1998-10-01), So
patent: 5887145 (1999-03-01), Harari
patent: 5973962 (1999-10-01), Kwon
patent: 5991202 (1999-11-01), Derhacobian
patent: 6011287 (2000-01-01), Itoh
patent: 6046935 (2000-04-01), Takeuchi
patent: 6049494 (2000-04-01), Sakui
patent: 6061270 (2000-05-01), Choi
patent: 6107658 (2000-08-01), Itoh
patent: 6181599 (2001-01-01), Gongwer
patent: 6456528 (2002-09-01), Chen
patent: 6493265 (2002-12-01), Satoh
patent: 6522580 (2003-02-01), Chen
patent: 6525964 (2003-02-01), Tanaka
patent: 6614688 (2003-09-01), Jeong
patent: 6643188 (2003-11-01), Tanaka
patent: 6859394 (2005-02-01), Matsunaga
patent: 6859395 (2005-02-01), Matsunaga
patent: 6859397 (2005-02-01), Lutze
patent: 7009881 (2006-03-01), Noguchi
patent: 7145806 (2006-12-01), Kawai
patent: 7161833 (2007-01-01), Hemink
patent: 7170793 (2007-01-01), Guterman
patent: 2004/0080980 (2004-04-01), Lee
patent: 2005/0237829 (2005-10-01), Nakamura et al.
patent: 2007/0171718 (2007-07-01), Hemink et al.
patent: 2007/0171719 (2007-07-01), Hemink et al.
S.Aritome, et al., “Reliability Issues of Flash Memory Cells,” Proceedings of the IEEE, New York, vol. 81, No. 5, May 1993, pp. 776-788.
Jung, et al., “A 3.3V 128Mb Multi-Level NAND Flash Memory for Mass Storage Applications,” ISSCC96, Session 2, Flash Memory, Paper TP 2.1, IEEE, pp. 32-33, slide supplement pp. 20-21, 346-347 (1996).
Jung, et al., “A 117-mm2 3.3-V Only 128-Mb Multilevel NAND Flash Memory for Mass Storage Applications,” IEEE Journal of Solid-State Circuits, vol. 31, No. 11, Nov. 1996, pp. 1575-1583.
A. Modelli, et al., “Basic Feasibility Constraints for Multilevel CHE-Programmed Flash Memories,” IEEE Trans. on Electron Devices, vol. 48, No. 9, Sep. 2001, pp. 2032-2042.
T. Nozaki, et al., “A 1-Mb EEPROM with MONOS Memory Cell for Semiconducor Disk Application,” IEEE Journal of Solid-State Circuits, vol. 26, No. 4, Apr. 1991, pp. 497-501.
K.D. Suh, et al., “A 3.3V 32Mb NAND Flash Memory with Incremental Step Pulse Programming Scheme,” IEEE Journal of Solid-State Circuits, vol. 30, No. 11, Nov. 1995, pp. 1149-1155.
U.S. Appl. No. 11/535,628, filed Sep. 27, 2006 entitled, “Reducing Program Disturb In Non-Volatile Storage,”.
U.S. Appl. No. 11/618,594, filed Dec. 29, 2006 entitled, “Systems For Programming Non-Volatile Memory With Reduced Program Disturb By Removing Pre-Charge Dependency On Word Line Data,”.
U.S. Appl. No. 11/618,600, filed Dec. 29, 2006 entitled, “Programming Non-Volatile Memory With Reduced Program Disturb By Using Different Pre-Charge Enable Voltages,”.
U.S. Appl. No. 11/618,606, filed Dec. 29, 2006 entitled, “Systems For Programming Non-Volatile Memory With Reduced Program Disturb By Using Different Pre-Charge Enable Voltages,”.
Non-final Office Action, United States Patent & Trademark Office, U.S. Appl. No. 11/618,600 filed on Dec. 29, 2006, Apr. 4, 2008.
Office Action (Ex Parte Quayle), United States Patent & Trademark Office, U.S. Appl. No. 11/618,606 filed on Dec. 29, 2006, Apr. 17, 2008.
Non-Final Office Action, United States Patent & Trademark Office, U.S. Appl. No. 11/618,594 filed on Dec. 29, 2006, Apr. 30, 2008.
Response to Non-Final Office Action, U.S. Appl. No. 11/618,594 filed Dec. 29, 2005, May 16, 2008.
Response to Non-Final Office Action, U.S. Appl. No. 11/618,600 filed Dec. 29, 2006, May 16, 2008.
Notice of Allowance and Fee(s) Due, United States Patent & Trademark Office, U.S. Appl. No. 11/618,594 filed on Dec. 29, 2006, Jun. 23, 2008.
Notice of Allowance and Fee(s) Due, United States Patent & Trademark Office, United States Patent & Trademark Office, U.S. Appl. No. 11/618,606 filed on Dec. 29, 2006, Jun. 19, 2008.
International Search Report & The Written Opinion of the International Searching Authority, Patent Cooperation Treaty, Application No. PCT/US2007/088931 filed on Dec. 27, 2007.
Dong Yingda
Hemink Gerrit Jan
Lee Dana
Lutze Jeffrey W.
Lam David
SanDisk Corporation
Vierra Magen Marcus & DeNiro LLP
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