Strain-silicon CMOS using etch-stop layer and method of...

Active solid-state devices (e.g. – transistors – solid-state diode – Thin active physical layer which is – Heterojunction

Reexamination Certificate

Rate now

  [ 0.00 ] – not rated yet Voters 0   Comments 0

Details

C257S018000, C257S063000, C257SE21576, C257SE21663, C257SE21635

Reexamination Certificate

active

07423283

ABSTRACT:
Recesses are formed in the drain and source regions of an MOS transistor. An ohmic contact layer is formed in the recesses, and a stressed silicon-nitride layer is formed over the ohmic contact layer. The recesses allow the stressed silicon nitride layer to provide strain in the plane of the channel region. In a particular embodiment, a tensile silicon nitride layer is formed over recesses of an NMOS transistor in a CMOS cell, and a compressive silicon nitride layer is formed over recesses of a PMOS transistor in the CMOS cell. In a particular embodiment the stressed silicon nitride layer(s) is a chemical etch stop layer.

REFERENCES:
patent: 5989986 (1999-11-01), Hsieh
patent: 6075262 (2000-06-01), Moriuchi et al.
patent: 6177319 (2001-01-01), Chen
patent: 6262445 (2001-07-01), Swanson et al.
patent: 6306712 (2001-10-01), Rodder et al.
patent: 6399973 (2002-06-01), Roberds
patent: 6541343 (2003-04-01), Murty et al.
patent: 6563152 (2003-05-01), Roberds et al.
patent: 6573172 (2003-06-01), En et al.
patent: 6713360 (2004-03-01), Jain et al.
patent: 6743684 (2004-06-01), Liu
patent: 6870179 (2005-03-01), Shaheed et al.
patent: 6939814 (2005-09-01), Chan et al.
patent: 7052964 (2006-05-01), Yeo et al.
patent: 7053400 (2006-05-01), Sun et al.
patent: 7132704 (2006-11-01), Grudowski
patent: 7193254 (2007-03-01), Chan et al.
patent: 7208362 (2007-04-01), Chidambaram
patent: 7256084 (2007-08-01), Lim et al.
patent: 7259105 (2007-08-01), Kim
patent: 7288448 (2007-10-01), Orlowski et al.
patent: 7314793 (2008-01-01), Frohberg et al.
patent: 2004/0104405 (2004-06-01), Huang et al.
patent: 2005/0040460 (2005-02-01), Chidambarrao et al.
patent: 2005/0136606 (2005-06-01), Rulke et al.
patent: 2005/0247975 (2005-11-01), Kim
patent: 2005/0247986 (2005-11-01), Ko et al.
patent: 2006/0009041 (2006-01-01), Iyer et al.
patent: 2006/0014350 (2006-01-01), Wang et al.
patent: 2006/0189167 (2006-08-01), Wang et al.
patent: 2006/0244074 (2006-11-01), Chen et al.
patent: 2007/0001217 (2007-01-01), Chen et al.
patent: 2007/0034963 (2007-02-01), Sudo
U.S. Appl. No. 11/095,814, filed Mar. 31, 2005, Nayak et al.
Pidin, S. et al., “A Novel Strain Enhanced CMOS Architecture Using Selectively Deposited High Tensile and High Compressive Silicon Nitride Films”, IEEE 2004, pp. 1-8, available from IEEE, 3 Park Avenue, 17th Floor, New York, NY 10016-5997.
Thompson, S. et al., A 90 nm Logic Technology Featuring 50 nm Strained Silicon Channel Transistors, 7 Layers Of Cu Interconnects, Low K ILD, and 1 um2 SRAM Cell, iedm 2002, pp. 1-32, available from Intel Corporation, www.intel.com/research/silicon.
Nayak, Deepak Kumar et al., “CMOS Device With Stressed Sidewall Spacers”, U.S. Appl. No. 11/221,507, filed Sep. 8, 2005, 17pages, available from Xilinx Inc., 2100 Logic Drive, San Jose, CA 95124.
Yuhao Luo, et al., “Semiconductor Device with Backfilled Isolation”, U.S. Appl. No. 11/244, 566, filed Oct. 6, 2005, 13 pages, available from Xilinx inc., 2100 Logic Drive, San Jose, CA 95124.
T. Ghani et al., “A 90nm High Volume Manufacturing Logic Technology featuring Novel 45nm Gate Lenght Strained Silicon CMOS Transistors”, IEEE, 2003, pp. 1-3, available from fahr.ghani@intel.com, or Intel Corporation (Santa Clara) Corporate Office, 2200 Mission College Blvd., Santa Clara, California 95052-8119, dated 2003.
Min Chin Chai, “90 nm Node CMOS Technology Comparison between Intel Corporation and Samsung Electronics”, pp. 1-6, May 8, 2003, available from Intel Corporation (Santa Clara) Corporate Office, 2200 Mission College Blvd., Santa Clara, California 95052-8119.
A. Brand et al., “Intel's 0.25 Micron, 2.0Volts Logic Process Technology”, pp. 1-9, available from Intel Corportion (Santa Clara) Corporate Office, 2200 Mission College Blvd., Santa Clara, California 95052-8119, dated; 1998.
B. P. R. Chidambaram et al., “35% Drive Current Imporvement from Recessed-SiGe Drain Extensions on 37 nm Gate Length PMOS”, 2004 Sumposium on VLSI Technology, Digest of Technical Paper, pp. 48-49, available form Texas Instruments, MS 3739, 13560 N. Central Expressway, Dallas, TX 75243; dated 2004.
Luo, Y. et al., “Enhancement of CMOS Performance by Process-Induced Stress”, IEEE Transactions on Seminconductors Manufacturing, vol. 18, No. 1, Feb. 2006, pp. 63-68.
U.S. Appl. No. 11/221,507, Nayak, D. K. et al., “CMOS Device With Sressed Sidewall Spacers”, filed Sep. 8, 2005, 13 pages, available form Xilinx Inc., 2100 Logic Drive, San Jose CA 95124.

LandOfFree

Say what you really think

Search LandOfFree.com for the USA inventors and patents. Rate them and share your experience with other people.

Rating

Strain-silicon CMOS using etch-stop layer and method of... does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Strain-silicon CMOS using etch-stop layer and method of..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Strain-silicon CMOS using etch-stop layer and method of... will most certainly appreciate the feedback.

Rate now

     

Profile ID: LFUS-PAI-O-3985396

  Search
All data on this website is collected from public sources. Our data reflects the most accurate information available at the time of publication.