Static information storage and retrieval – Addressing – Sync/clocking
Reexamination Certificate
2007-01-12
2008-09-02
Hoang, Huan (Department: 2827)
Static information storage and retrieval
Addressing
Sync/clocking
C365S233120, C365S233150, C365S233140, C365S227000
Reexamination Certificate
active
07420873
ABSTRACT:
A power-down control circuit utilizes the control signals employed in an active mode operation to operate when a power-down mode entry command is received during an active mode operation. The circuit is simplified requiring less area for devising the control circuit while lowering power consumption. The power-down control circuit in a semiconductor memory device includes at least a clock enable buffer unit, an external clock buffer unit, a latch unit, a control circuit for controlling internally operating clocks employed in active mode operation by using a control signal used in the active mode operation when a power-down mode entry command is received during the active mode operation, and a clock enable generation circuit for outputting clock enable signals for enabling entry to the power-down mode by using the clock control signals, when the external clock pulse signal is low level.
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Korean Patent Gazette, Feb. 9, 2007.
Hoang Huan
Hynix / Semiconductor Inc.
Ladas & Parry LLP
Weinberg Michael J
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