Tape wiring substrate and chip-on-film package using the same

Details Tape wiring substrate and chip-on-film package using the same Tape wiring substrate and chip-on-film package using the same

2006-02-28

2008-09-02

Dang, Trung (Department: 2892)

Active solid-state devices (e.g., transistors, solid-state diode

Housing or package

With contact or lead

C257S698000, C257SE23065, C257SE23070

Reexamination Certificate

active

07420270

ABSTRACT:
A chip-on-film package may include a tape wiring substrate, a semiconductor chip mounted on the tape wiring substrate, and a molding compound provided between the semiconductor chip and the tape wiring substrate. The tape wiring substrate may include a film having upper and lower surfaces. Vias may penetrate the film. An upper metal layer may be provided on the upper surface of the film and include input terminal patterns and/or output terminal patterns. The input terminal patterns may include ground terminal patterns and/or power terminal patterns. A lower metal layer may be provided on the lower surface of the film and include a ground layer and/or a power layer. The ground layer and the power layer may cover at least a chip mounting area.

REFERENCES:
patent: 6864119 (2005-03-01), Seko
patent: 2003/0058530 (2003-03-01), Ide
patent: 2004/0145052 (2004-07-01), Ueno et al.
patent: 2005/0093114 (2005-05-01), Son et al.
patent: 2005/0218512 (2005-10-01), Egawa et al.
patent: 2007/0094872 (2007-05-01), Konishi et al.
patent: 07-094555 (1995-04-01), None
patent: 2001-102406 (2001-04-01), None
patent: 10-2003-0037168 (2003-05-01), None

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