Non-volatile memory cells in a field programmable gate array

Details Non-volatile memory cells in a field programmable gate array Non-volatile memory cells in a field programmable gate array

2007-10-08

2008-09-30

Hur, J. H. (Department: 2824)

Static information storage and retrieval

Floating gate

Particular connection

C365S188000, C365S189020, C365S230020, C326S038000, C326S039000, C326S044000, C326S049000

Reexamination Certificate

active

07430137

ABSTRACT:
A non-volatile memory cell comprises a first floating gate transistor having a source, a drain, and a gate electrically coupled to a row line. A second floating gate transistor has a source, a drain, and a gate electrically coupled to the row line. A first p-channel MOS transistor has a source, a drain, and a gate, the drain of the first p-channel MOS transistor electrically coupled to the drain of the first floating gate transistor forming a first common node. A second p-channel MOS transistor has a source, a drain, and a gate, the first drain of the second p-channel MOS transistor electrically coupled to the drain of the second floating gate transistor forming a second common node, the gate of the second p-channel MOS transistor electrically coupled to the first common node, and the second common node electrically coupled to the gate of the first p-channel MOS transistor.

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