Memory array with staged output

Details Memory array with staged output Memory array with staged output

2005-12-23

2008-03-25

Hoang, Huan (Department: 2827)

Static information storage and retrieval

Addressing

Plural blocks or banks

C365S194000, C365S189050

Reexamination Certificate

active

07349284

ABSTRACT:
Embodiments of the present invention provide a method and system for staging the data output from an addressable memory location as a plurality of fields. In embodiments, each field of a data item that is stored at an address may be output during a different clock cycle. In further embodiments, the most time critical field may be output first.

REFERENCES:
patent: 5978303 (1999-11-01), Takasugi et al.
patent: 6097657 (2000-08-01), Ng et al.
patent: 6778530 (2004-08-01), Greene

Affiliated with

Also associated with

Rating

Memory array with staged output does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Memory array with staged output, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Memory array with staged output will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-3977654