Method and apparatus for statistical CMOS device...

Electricity: measuring and testing – Fault detecting in electric circuits and of electric components – Of individual circuit component or element

Reexamination Certificate

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Reexamination Certificate

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07397259

ABSTRACT:
A unified test structure having a large number of electronic devices under test is used to characterize both capacitance-voltage parameters (C-V) and current-voltage parameters (I-V) of the devices. The devices are arranged in an array of columnns and rows, and selected by control logic which gates input/output pins that act variously as current sources, sinks, clamps, measurement ports and sense lines. The capacitance-voltage parameter is measured by taking baseline and excited current measurements for different excitation voltage frequencies, calculating current differences between the baseline and excited current measurements, and generating a linear relationship between the current differences and the different frequencies. The capacitance is then derived by dividing a slope of a line representing the linear relationship by the excitation voltage. Different electronic devices may be so tested, including transistors and interconnect structures.

REFERENCES:
patent: 7208759 (2007-04-01), Momohara
patent: 7336085 (2008-02-01), Fabbro et al.
U.S. Appl. No. 11/422,913, K. Agarwal et al.
L. Vendrame et al., “Crosstalk-Based Capacitance Measurements; Theory And Applications,” IEEE Transactions on Semiconductor Manufacturing, vol. 19, No. 1, Feb. 2006.
B. McGaughy et al., “A Simple Method for On-Chip Sub-Femto-Farad Interconnect Capacitance Measurement,” IEEE Electron Device Letters, vol. 18, No. 1 (Jan. 1997).

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