Semiconductor memory device having a global data bus

Details Semiconductor memory device having a global data bus Semiconductor memory device having a global data bus

2007-04-24

2008-07-01

Elms, Richard T. (Department: 2824)

Static information storage and retrieval

Addressing

Plural blocks or banks

C365S230050, C365S239000

Reexamination Certificate

active

07394718

ABSTRACT:
There is provided a semiconductor design technology, particularly, a bus line arrangement method of global data bus in the semiconductor memory device. According to the invention, skew by lines can be not occurred, or can be minimized upon an issuance thereof. Further, upon its issuance, it is easy to compensate it relying on the specific rule. The present invention proposes a scheme that classifies data transmission units corresponding to each bank into plural groups, each group having some continuous data transmission units, and makes bus lines of the global data bus to be arranged alternately for each group. In other words, the global data bus line arrangement scheme suggested by the present invention may be defined as grouped alternate arrangement scheme. In this case, the overlap interval between adjacent global data bus lines can be reduced largely and skew problem by lines can also be solved.

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