Process for fabricating chip embedded package structure

Details Process for fabricating chip embedded package structure Process for fabricating chip embedded package structure

2005-12-27

2008-07-29

Coleman, W. David (Department: 2823)

Semiconductor device manufacturing: process

Packaging or treatment of packaged semiconductor

Assembly of plural semiconductive substrates each possessing...

C438S015000, C438S026000, C438S055000, C257SE21499, C257SE21505, C257SE21516

Reexamination Certificate

active

07405103

ABSTRACT:
A process for fabricating a chip embedded package structure is provided. A stiffener is disposed on a tape. A chip is disposed on the tape inside a chip opening of the stiffener such that an active surface of the chip faces the tape. Through holes are formed passing the tape and exposing bonding pads of the chip on the active surface respectively. Conductive material is deposited into the though holes to form a plurality of conductive vias which are connected to the bonding pads respectively. A multi-layered interconnection structure is formed on the tape on the opposite of the chip, wherein the multi-layered interconnection structure comprises an inner circuit which is connected to the conductive vias, and the inner circuit has a plurality of metallic pads on a surface of the multi-layered interconnection structure away from the tape.

REFERENCES:
patent: 6864165 (2005-03-01), Pogge et al.
patent: 7026079 (2006-04-01), Louwet et al.
patent: 2002/0127769 (2002-09-01), Ma et al.
patent: 2002/0197767 (2002-12-01), Saia et al.
patent: 2004/0119166 (2004-06-01), Sunohara

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