Static information storage and retrieval – Addressing – Sync/clocking
Patent
1997-03-04
1998-08-11
Nelms, David C.
Static information storage and retrieval
Addressing
Sync/clocking
365206, G11C 800
Patent
active
057936994
ABSTRACT:
A circuit for generating and resetting timing signals used for reading a memory device, includes first detecting circuit means for detecting a state transition of address digital signals of the memory device, the detecting means being suitable of generating a start digital signal of a read operation represented by a digital pulse of a prescribed duration upon a state transition of at least one of said address signals, second circuit means activated by said start signal for generating a timing signal for the read operation of the memory device, and third circuit means driven by said start digital signal for generating resetting signals for said timing signals, and fourth circuit means for detecting than said start signal has a duration shorter that said prescribed duration and for determining a consequent extension of the duration of said start signal sufficient to assure the generation of said resetting signals.
REFERENCES:
patent: 5323359 (1994-06-01), Kayamoto et al.
patent: 5418479 (1995-05-01), Sambandan
patent: 5654935 (1997-08-01), Hisada et al.
patent: 5657269 (1997-08-01), Nanamiya
Ho Hoai
Nelms David C.
SGS--Thomson Microelectronics S.r.l.
LandOfFree
Circuit for the generation and reset of timing signal used for r does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Circuit for the generation and reset of timing signal used for r, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Circuit for the generation and reset of timing signal used for r will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-396527