Semiconductor memory device having level-shifted precharge signa

Details Semiconductor memory device having level-shifted precharge signa Semiconductor memory device having level-shifted precharge signa

1996-08-14

1998-08-11

Nelms, David C.

Static information storage and retrieval

Addressing

Particular decoder or driver circuit

36518911, G11C 700

Patent

active

057936951

ABSTRACT:
A semiconductor memory device comprising a plurality of row decoders, each having a precharge circuit connected to receive a precharge signal and a decode circuit connected to receive address signals. A level-shifted precharge signal is input to the precharge circuits.

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Gillingham et al., "High-Speed, High-Reliability Circuit Design for Megabit DRAM"; IEEE J. of Solid-State Circuits, vol. 26, No. 8, Aug. 1991, pp. 1171-1175.
Komatsuzaki et al., Circuit Techniques for a Wide Word I/O Path 64 Meg DRAM; 1991 VISI Synp., Circuits 14-5, pp. 133-134.

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