Method of making high voltage PNP bipolar transistor in CMOS

Details Method of making high voltage PNP bipolar transistor in CMOS Method of making high voltage PNP bipolar transistor in CMOS

1993-01-04

1994-07-12

Chaudhuri, Olik

Fishing, trapping, and vermin destroying

437 74, 437 59, 148DIG11, 257339, H01L 21265, H01L 2970

Patent

active

053288599

ABSTRACT:
A high voltage bipolar transistor fabricated on a CMOS substrate without adding any additional process steps. During the CMOS n-well mask and implant steps an n-well is formed for the transistor. Next, during the CMOS field and deep boron implant steps a circular p-field is formed within the n-well. Finally, during the CMOS p+ mask and implant steps the p+ emitter is formed. The presence of the p-field between the emitter and n+ base provides high voltage protection.

REFERENCES:
patent: 5229308 (1993-07-01), Vo et al.

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