System and method for matching chip and package terminals

Details System and method for matching chip and package terminals System and method for matching chip and package terminals

2005-06-30

2008-03-04

Picardat, Kevin M. (Department: 2822)

Semiconductor device manufacturing: process

With measuring or testing

Packaging or treatment of packaged semiconductor

C438S016000, C438S108000

Reexamination Certificate

active

07338819

ABSTRACT:
A system and method for matching chip and package terminals and for packaging integrated circuits. Various aspects of the present invention may comprise receiving as input a first list of chip terminal identifiers and a second list of package terminal identifiers. The first and second lists may be analyzed with a first string-matching algorithm to determine a first set of matching pairs of chip terminals and package terminals. The first and second lists may also be analyzed with a second string-matching algorithm to determine a second set of matching pairs of chip terminals and package terminals. The first and second sets of matching pairs may be compared to identify common matching pairs between the first and second sets of matching pairs. An indication of the common matching pairs may then be output.

REFERENCES:
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patent: 5694482 (1997-12-01), Maali et al.
patent: 6684402 (2004-01-01), Wolff
patent: 6900459 (2005-05-01), Farnworth et al.
patent: 7071078 (2006-07-01), Reeder et al.
patent: 04279973 (1992-10-01), None
patent: WO 2004/079631 (2004-09-01), None

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