System and method of identifying the number of chip failures on

Details System and method of identifying the number of chip failures on System and method of identifying the number of chip failures on

1995-10-19

1998-08-11

Voeltz, Emanuel T.

Boots, shoes, and leggings

36446816, 36446828, 437 8, 324765, G01R 3126

Patent

active

057936501

ABSTRACT:
A method of identifying the non-clustered failure yield on a wafer which includes: measuring an absolute yield of the chips on a wafer; identifying a first set of clustered failed chips in which each failed chip is disposed in a field of chips whose yield is below the absolute yield; determining an adjusted yield discounted for the first set of clustered failed chips; identifying at least one additional set of clustered failed chips in which each failed chip is disposed in a field of chips whose yield is below the adjusted yield; and determining an additional adjusted yield for each additional set of clustered failed chips discounting for the previous set of clustered failed chips until the difference between the additional adjusted yield and the previous adjusted yield are within a predetermined maximum acceptable difference for indicating a non-clustered failure yield of the wafer.

REFERENCES:
patent: T959005 (1977-06-01), Froot et al.
patent: 3615466 (1971-10-01), Sahni
patent: 3751647 (1973-08-01), Maeder et al.
patent: 4144493 (1979-03-01), Lee et al.
patent: 5047947 (1991-09-01), Stump
patent: 5351202 (1994-09-01), Kurtzberg et al.
patent: 5394348 (1995-02-01), Abe
patent: 5396433 (1995-03-01), Kosugi et al.
patent: 5539652 (1996-07-01), Tegethoff
patent: 5598341 (1997-01-01), Ling et al.
Stapper et al., "integrated Circuit Yield Statistics", Proceedings of the IEEE, vol. 71, No. 4, Apr. 1983, pp. 453-469.
Tyagi et al., "Defect Clustering Viewed Through Generalized Poisson Distribution", IEEE Transactions on Semiconductor Manufacturing, vol. 5, No. 3, Aug. 1992, pp. 196-206.
Randall S. Collica, "The Effect of the Number of Defect Mechanisms on Fault Clustering and its Detection Using Yield Model Parameters", IEEE Transactions on Semiconductor Manufacturing, vol. 5, No. 3, Aug. 1992, 189-195.
James A. Cunningham, "The Use and Evaluation of Yield Models in Integrated Circuit Manufacturing", IEEE Transactions on Semiconductor Manufacturing, vol. 3, No. 2, May 1990. pp. 60-71.
De Gyvez et al., "On the Design and Implementation of a Wafer Yield Editor", IEEE Transactions on Computer-Aided Design, vol. 8, No. 8, Aug. 1989, pp. 920-925.
John Shier, "A Statistical Model for Integrated-Circuit Yield with Clustered Flaws", IEEE Transactions on Electron Devices, vol. 35, No. 4, Apr. 1988, pp. 524-525.

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