High frequency circuit capable of error detection and...

Electrical pulse counters – pulse dividers – or shift registers: c – Systems – Identifying or correcting improper counter operation

Reexamination Certificate

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C377S028000, C714S037000, C714S040000

Reexamination Certificate

active

10988285

ABSTRACT:
A method, an apparatus, and a computer program are provided for generating an error detection state and correction of code patterns. Generally, conducting full speed testing of the dI/dt circuit in a low bandwidth lab environment is difficult. A circuit, however, can be employed that periodically detects the functionality of the dI/dt circuit to indicate success or failure. When errors are detected, the circuit allows for erroneous codes to be replaced with accurate ones. Using this circuit, conducting full speed testing of the dI/dt circuit in a low bandwidth lab environment can be more easily achieved.

REFERENCES:
patent: 3331953 (1967-07-01), Rouzier
patent: 6486717 (2002-11-01), Kinoshita et al.
patent: 6950490 (2005-09-01), Koh et al.
patent: 02121411 (1990-05-01), None
Stan, M.R.; Synchronous up/down counter with clock period independent of counter size; Computer Arithmetic, 1997. Proceedings., 13th IEEE Symposium on; Jul. 6-9, 1997; pp. 274-281.

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