Metal working – Barrier layer or semiconductor device making
Reexamination Certificate
2008-05-20
2008-05-20
Estrada, Michelle (Department: 2823)
Metal working
Barrier layer or semiconductor device making
C438S618000, C438S976000
Reexamination Certificate
active
11783186
ABSTRACT:
The present invention provides an interconnects-forming method and an interconnects-forming apparatus which can minimize the lowering of processing accuracy in etching, minimize light exposure processing for the formation of interconnect recesses in the production of multi-level interconnects, improve the electromigration resistance of interconnects without impairing the electrical properties of the interconnects, and enhance the reliability of the device. The interconnects-forming method, includes providing interconnect recesses in an insulating film formed in a surface of a substrate; embedding an interconnect material in the interconnect recesses while forming a metal film of the interconnect material on a surface of the insulating film; removing an extra metal material other than the metal material in the interconnect recesses and flattening the substrate surface, thereby forming interconnects; forming a first protective film of a conductive material selectively on exposed surfaces of the interconnects; forming a second protective film on the surface of the substrate having the thus-formed first protective film; forming an interlevel insulating film on the surface of the substrate having the thus-formed second protective film; and flattening a surface of the interlevel insulating film.
REFERENCES:
patent: 5674787 (1997-10-01), Zhao et al.
patent: 5695810 (1997-12-01), Dubin et al.
patent: 6144099 (2000-11-01), Lopatin et al.
patent: 6265328 (2001-07-01), Henley et al.
patent: 6267853 (2001-07-01), Dordi et al.
patent: 6294059 (2001-09-01), Hongo et al.
patent: 6734559 (2004-05-01), Yang et al.
patent: 6833318 (2004-12-01), Weng et al.
patent: 6838370 (2005-01-01), Niuya et al.
patent: 6905964 (2005-06-01), Lim et al.
patent: 7008872 (2006-03-01), Dubin et al.
patent: 7064065 (2006-06-01), Lopatin et al.
patent: 2003/0109129 (2003-06-01), Saito et al.
patent: 2003/0214043 (2003-11-01), Saitoh et al.
patent: 2003/0221612 (2003-12-01), Dai et al.
Fukunaga Akira
Fukunaga Yukio
Takagi Daisuke
Tashiro Akihiko
Wang Xinming
Ebara Corporation
Estrada Michelle
Wenderoth , Lind & Ponack, L.L.P.
LandOfFree
Interconnects forming method and interconnects forming... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Interconnects forming method and interconnects forming..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Interconnects forming method and interconnects forming... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-3956957