Semiconductor memory device capable of setting a negative...

Details Semiconductor memory device capable of setting a negative... Semiconductor memory device capable of setting a negative...

2008-04-29

2008-04-29

Lam, David (Department: 2827)

Static information storage and retrieval

Floating gate

Particular biasing

C365S185170, C365S203000

Reexamination Certificate

active

11300364

ABSTRACT:
In a memory cell array, a plurality of memory cells connected to word lines and bit lines are arranged in a matrix. A control circuit controls the potentials of the word lines and bit lines. The control circuit, when reading data from the memory cell connected to a first one of the bit lines, supplies a first voltage to a second bit line provided next to the first bit line and to a source line of the memory cell array.

REFERENCES:
patent: 5253206 (1993-10-01), Tanaka et al.
patent: 6195291 (2001-02-01), Dallabora et al.
patent: 6813187 (2004-11-01), Lee
patent: 6888756 (2005-05-01), Byeon et al.
patent: 7031197 (2006-04-01), Yoshida
patent: 2004/0170056 (2004-09-01), Shibata et al.
patent: 2005/0035393 (2005-02-01), Lung et al.
patent: 2006/0133150 (2006-06-01), Shibata
patent: 3-283200 (1991-12-01), None
patent: 2004-192789 (2004-07-01), None
U.S. Appl. No. 11/457,320, filed Jul. 13, 2006, Shibata et al.
U.S. Appl. No. 11/737,413, filed Apr. 19, 2007, Shibata.

Affiliated with

Also associated with

Rating

Semiconductor memory device capable of setting a negative... does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Semiconductor memory device capable of setting a negative..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Semiconductor memory device capable of setting a negative... will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-3955709