Method for forming dielectrically isolated PMOS, NMOS, PNP and N

Details Method for forming dielectrically isolated PMOS, NMOS, PNP and N Method for forming dielectrically isolated PMOS, NMOS, PNP and N

1986-04-29

1987-08-11

Hearn, Brian E.

Fishing, trapping, and vermin destroying

357 231, 357 43, 357 50, 357 56, 437 56, 437 81, 437235, 437 62, H01L 2170

Patent

active

046851992

ABSTRACT:
A plurality of monocrystalline silicon seeds is disposed on an insulator layer which is disposed on a substantially flat major surface of a silicon wafer. A first monocrystalline silicon deposit of first conductivity type is formed on a first silicon seed and a second monocrystalline silicon deposit, of similar configuration, is formed on a second silicon seed. The first and second deposits are then covered with insulator layers and a third monocrystalline deposit is formed on a third silicon seed. The third deposit has a top surface height substantially equal to or less than that of the top surfaces of the first and second deposits. An insulator layer is then formed on the top surface of the third deposit and first and second monocrystalline islands are formed on this insulator layer. Complementary bipolar transistors are formed in the first and second monocrystalline silicon deposits and PMOS and NMOS transistors are formed in the first and second islands on the third insulator layer.

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Applied Solid State Science, Supplement 2, Part A, edited by Dawon Kahng, Academic Press, 1981, pp. 310-336.

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