Method of manufacturing isolated semiconductor devices

Details Method of manufacturing isolated semiconductor devices Method of manufacturing isolated semiconductor devices

1985-07-25

1987-08-11

Hearn, Brian E.

Fishing, trapping, and vermin destroying

148DIG50, 148DIG115, 156647, 156644, 357 49, H01L 2906

Patent

active

046851984

ABSTRACT:
Disclosed is a method of isolating a transistor perfectly by employing a selective oxidation technology (LOCOS technology). More particularly, vertical openings are formed in the surface of {100} silicon substrate, and oxidation resistant films are formed of this surface and in part of the side walls of these openings. In succession, by etching with an etchant having an orientation anisotropy, dents are formed at high precision in the side walls of the openings. By oxidizing using the oxidation resistant film as the mask, an oxide film growing out from a dent in the opening side wall is connected with another oxide film growing out from an adjacent dent. The transistor thus formed in the active region of the silicon electrically isolated from the substrate is small in parasitic capacitance and may be formed into a small size, so that it possesses the features suited to VLSI, that is, high speed, low power consumption, and processability to high density integration.

REFERENCES:
patent: 4104090 (1978-08-01), Pogge
patent: 4437226 (1984-03-01), Soclof
patent: 4485551 (1984-12-01), Soclof
patent: 4520552 (1985-06-01), Arnould et al.
Nicholas et al, "Dielectric Isolation by Orientation-Dependent Etching", Electronic Letters, 20(24), 11/22/84.

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