Method for making planar FET having gate, source and drain in th

Details Method for making planar FET having gate, source and drain in th Method for making planar FET having gate, source and drain in th

1985-07-29

1987-08-11

Roy, Upendra

Fishing, trapping, and vermin destroying

148DIG82, 156628, 156643, 357 239, 357 2314, 437203, 437 20, H01L 21263, H01L 21306, H01L 736

Patent

active

046851968

ABSTRACT:
An MOS transistor with a trench channel and self-aligned source and drain contacts to the interconnection layer. The MOS transistor is fabricated by first etching the substrate of monocrystalline silicon so as to form a trench channel and thereafter filling the trench channel with an anisotropic etched first polycrystalline silicon film. Buried contacts of polycrystalline silicon to the substrate, and Al-Si metallization are used. The trench structure in the channel regions permits the self-alignment of the gate element and the buried contacts to source and drain regions. The MOS transistors of the invention significantly reduce the short channel effect as observed in conventional MOS transistors.

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G. Merckel, "Short Channels-Scaled Down MOSFET's", pp. 705-725 of Process and Device Modeling for IC Design, 1977, ed. F. VandeWiele et al.
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S. Nishimatsu et al. "Grooved Gate MOSFET" in Japanese J. of Applied Physics, vol. 16, Supp. 16-1 (1977) 179-183.

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