Supply voltage characteristic measurement

Electricity: measuring and testing – Measuring – testing – or sensing electricity – per se – Frequency of cyclic current or voltage

Reexamination Certificate

Rate now

  [ 0.00 ] – not rated yet Voters 0   Comments 0

Details

C324S076110, C327S158000

Reexamination Certificate

active

11240687

ABSTRACT:
For one disclosed embodiment, a delay is to receive signals and to delay received signals for an amount of time at least partially dependent on a supply voltage to generate delayed signals. Logic is to help measure a characteristic relating to the supply voltage based at least in part on the delayed signals. Other embodiments are also disclosed.

REFERENCES:
patent: 4164648 (1979-08-01), Chu
patent: 5489466 (1996-02-01), Inaba et al.
patent: 5590341 (1996-12-01), Matter
patent: 5663991 (1997-09-01), Kelkar et al.
patent: 5703838 (1997-12-01), Gorbics et al.
patent: 5793822 (1998-08-01), Anderson et al.
patent: 6295315 (2001-09-01), Frisch et al.
patent: 6421794 (2002-07-01), Chen et al.
patent: 6448754 (2002-09-01), Ihs et al.
patent: 6657467 (2003-12-01), Seki et al.
patent: 6670800 (2003-12-01), Beach et al.
patent: 6747470 (2004-06-01), Muhtaroglu et al.
patent: 6777921 (2004-08-01), Abdennadher et al.
patent: 6822491 (2004-11-01), Glass
patent: 6836872 (2004-12-01), Abdennadher
patent: 6868534 (2005-03-01), Fattouh et al.
patent: 2002/0190283 (2002-12-01), Seno et al.
patent: 2003/0112027 (2003-06-01), Muhtaroglu et al.
patent: 2003/0141859 (2003-07-01), Abdennadher et al.
patent: 2003/0177427 (2003-09-01), Fattouh et al.
patent: 2003/0210028 (2003-11-01), Beach et al.
patent: 2004/0060017 (2004-03-01), Abdennadher
patent: 2004/0085085 (2004-05-01), Mahtaroglu et al.
patent: 2004/0128591 (2004-07-01), Ihs et al.
Abdennadher, Salem, et al., “Mixed Signal DFT/BIST Automation Using Behavioral Modeling”, 2001 Southwest Symposium on Mixed-Signal Design (SSMSD), pp. 137-140 (Feb. 25-27, 2001).
Abdennadher, Salem, “Flow for Phase Locked Loop Mixed Signal Simulation and Characterization Using Behavioral Modeling”, 2003 Southwest Symposium on Mixed-Signal Design (SSMSD), pp. 66-70 (Feb. 23-25, 2003).
Alon, Elad, et al., “Circuits and Techniques for High-Resolution Measurement of On-Chip Power Supply Noise”, 2004 Symposium on VLSI Circuits, Digest of Technical Papers, pp. 102-105 (Jun. 17-19, 2004).
Alon, Elad, et al., “Circuits and Techniques for High-Resolution Measurement of On-Chip Power Supply Noise”, IEEE Journal of Solid-State Circuits, vol. 40, No. 4, pp. 820-828 (Apr. 2005).
Arabi, Karim, et al., “Digital Oscillation-Test Method for Delay and Stuck-at Fault Testing of Digital Circuits”, Proceedings of the International Test Conference, pp. 91-100 (Oct. 18-23, 1998).
Arabi, K., et al., “Dynamic Digital Integrated Circuit Testing Using Oscillation-Test Method”, Electronics Letters, vol. 34, No. 8, pp. 762-764 (Apr. 16, 1998).
Desai, Utpal, et al., “Itanium Processor Clock Design”, Proceedings of the 2000 International Symposium on Physical Design (ISPD), pp. 94-98 (May 2000).
Dufaza, C., et al., “Boolean Equations for Multiple Paths Sensitisation of Digital Oscillation Built-In Self Test”, Electronics Letters, vol. 34, No. 23, pp. 2213-2215 (Nov. 12, 1998).
Fischer, Tim, et al., “A 90nm Variable-Frequency Clock System for a Power-Managed Itanium-Family Processor”, 2005 IEEE International Solid-State Circuits Conference (ISSCC), Digest of Technical Papers, vol. 1, pp. 294-295 & 599 (Feb. 6-10, 2005).
Muhtaroglu, Ali, et al., “On-Die Droop Detector for Analog Sensing of Power Supply Noise”, 2003 Symposium on VLSI Circuits, Digest of Technical Papers, pp. 193-196 (Jun. 12-14, 2003).
Muhtaroglu, Ali, et al., “On-Die Droop Detector for Analog Sensing of Power Supply Noise”, IEEE Journal of Solid-State Circuits, vol. 39, No. 4, pp. 651-660 (Apr. 2004).
Sunter, Stephen, et al., “BIST for Phase-Locked Loops in Digital Applications”, Proceedings of the International Test Conference, pp. 532-540 (Sep. 28-30, 1999).
Sunter, Stephen, et al., “On-Chip Digital Jitter Measurement, from Megahertz to Gigahertz”, IEEE Design & Test of Computers, vol. 21, No. 4, pp. 314-321 (Jul.-Aug. 2004).
Takamiya, Makoto, et al., “An On-chip 100GHz-Sampling Rate 8-channel Sampling Oscilloscope with Embedded Sampling Clock Generator”, 2002 IEEE International Solid-State Circuits Conference (ISSCC), Digest of Technical Papers, vol. 1, pp. 182-183 & 458 (Feb. 3-7, 2002).
Takamiya, Makoto, et al., “An On-Chip 100GHz-Sampling 8-channel Sampling Oscilloscope with Embedded Sampling Clock Generator”, 2002 IEEE International Solid-State Circuits Conference (ISSCC), Digest of Technical Papers, vol. 2, pp. 140-141 & 439 (Feb. 3-7, 2002).
Takamiya, Makoto, et al., “On-Chip Jitter-Spectrum-Analyzer for High-Speed Digital Designs”, 2004 IEEE International Solid-State Circuits Conference (ISSCC), Digest of Technical Papers, vol. 1, pp. 350-532 (Feb. 15-19, 2004).

LandOfFree

Say what you really think

Search LandOfFree.com for the USA inventors and patents. Rate them and share your experience with other people.

Rating

Supply voltage characteristic measurement does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Supply voltage characteristic measurement, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Supply voltage characteristic measurement will most certainly appreciate the feedback.

Rate now

     

Profile ID: LFUS-PAI-O-3953143

  Search
All data on this website is collected from public sources. Our data reflects the most accurate information available at the time of publication.