Semiconductor memory device layout comprising high impurity...

Details Semiconductor memory device layout comprising high impurity... Semiconductor memory device layout comprising high impurity...

Filed on

2008-01-15

Date issued

2008-01-15

Examiner

Nguyen, Van Thu (Department: 2824)

Patent Class

Static information storage and retrieval

SubClass

Format or disposition of elements

Other Related Categories

C365S063000, C365S154000, C257S390000

Type

Reexamination Certificate

Status

active

Patent number

11242054

Description

ABSTRACT:
A semiconductor device includes a plurality of memory cells, and an error-correction circuit. Its write operation is performed by a late-write method, and ECC processing is executed in parallel with writing to shorten a cycle time. Moreover, when a memory cell is power-supplied through a well tap, the same address is not assigned while the memory cell is power-supplied through the well tap.

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patent: 6347062 (2002-02-01), Nii et al.
patent: 6711067 (2004-03-01), Kablanian
patent: 6714471 (2004-03-01), Kono
patent: 6885609 (2005-04-01), Lee et al.
patent: 61-50295 (1984-08-01), None
patent: 7-45096 (1993-08-01), None

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