Two-bit per I/O line write data bus for DDR1 and DDR2...

Details Two-bit per I/O line write data bus for DDR1 and DDR2... Two-bit per I/O line write data bus for DDR1 and DDR2...

2008-03-25

2008-03-25

Hur, J. H. (Department: 2824)

Static information storage and retrieval

Addressing

Sync/clocking

C365S194000, C365S198000, C365S219000, C365S193000, C365S189050

Reexamination Certificate

active

11177537

ABSTRACT:
A data bus circuit for an integrated circuit memory includes a 4-bit bus per I/O pad that is used to connect the memory with an I/O block, but only two bits per I/O are utilized for writing. Four bits per I/O pad are used for reading. At every falling edge of an input data strobe, the last two bits are transmitted over the bus, which eliminates the need for the precise counting of input data strobe pulses. The data bus circuit is compatible with both DDR1 and DDR2 operating modes.

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