Glitch free clock multiplexer that uses a delay element to...

Details Glitch free clock multiplexer that uses a delay element to... Glitch free clock multiplexer that uses a delay element to...

2008-05-20

2008-05-20

Lam, Tuan T (Department: 2816)

Miscellaneous active electrical nonlinear devices, circuits, and

Signal converting, shaping, or generating

Clock or pulse waveform generating

C327S099000

Reexamination Certificate

active

11445851

ABSTRACT:
A clock multiplexer circuit uses a delay element to detect a transition-free period in a first signal present on a D-input lead of an output latch. The output latch is then controlled to latch the stable value of the first signal, and to hold the value of the first signal on an output lead of the clock multiplexer circuit. The clock multiplexer circuit then controls a multiplexer of the clock multiplexer circuit to couple a second signal onto the D-input lead of the output latch. The clock multiplexer circuit then enables the output latch synchronously with respect to the second signal such that the output latch is made transparent at a time when the second signal on the D-input of the output latch is stable and not transitioning. The result is glitch free clock switching from the first signal to the second signal.

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IBM Technical Disclosure, Gartmann et al., “Method To Select One Of Two Clocks While Avoiding Narrow Pulses,” vol. 32 No. 98, Feb. 1990, pp. 82-84, printout from Delphion.

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