Voltage controlled oscillator formed of two differential transco

Oscillators – Ring oscillators

Patent

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Details

331115, 331132, 331135, 331177R, H03B 500

Patent

active

056358792

ABSTRACT:
A monolithic CMOS phase-lock loop (PLL) circuit provides a high frequency of operation suitable for RF applications. The PLL produces an output clock with high spectral purity and very low jitter. The output clock has a low static phase error relative to a reference input, making the PLL also useful for clock synchronizing applications, such as clock recovery elements in transmission/recycling channels. The PLL provides in-phase and quadrature signals from a VCO which has two differential transconductor stages having negative output conductance.

REFERENCES:
patent: 5117205 (1992-05-01), Nauta

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