System and method for achieving buffer memory coincidence in a m

Details System and method for achieving buffer memory coincidence in a m System and method for achieving buffer memory coincidence in a m

1978-10-30

1981-09-15

Atkinson, Charles E.

Boots, shoes, and leggings

G06F 1300

Patent

active

042901030

ABSTRACT:
Effective expansion of a common intermediate buffer memory by equivalent use of the buffer memory in each CPU in a multiprocessor system. A method and system for achieving buffer memory coincidence is applied to a multiprocessor system provided with central processing units, buffer memories contained in respective central processing units, a main memory, and an intermediate buffer memory connected between the main memory and the buffer memories, wherein a buffer invalidation address information (BIA GO) is sent from the intermediate buffer memory to the i-th central processing unit (BIA GO #i) in accordance with the following logical expression:

REFERENCES:
patent: 4056844 (1977-11-01), Izumi
patent: 4136386 (1979-01-01), Annunziata et al.
patent: 4142234 (1979-02-01), Bean
R. Meade, "On Memory System Design", F.J.C.C., 1970, pp. 33-38.

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