High speed digital motion controller architecture

Details High speed digital motion controller architecture High speed digital motion controller architecture

1989-02-17

1990-12-11

MacDonald, Allen R.

Boots, shoes, and leggings

364132, 364513, 36447411, 3185682, G05B 1100, G11C 1300

Patent

active

049774948

ABSTRACT:
A system bus (13) carrying multidimensional path data interfaces with a plurality of local microprocessors (24), one for each dimension, through a plurality of dual access memory structures (21), one for each local microprocessor (24). A local arbiter (35) controls access to each dual access memory structure (21), facilitating elimination of wait states in data transfers between the bus (13) and memory (21) and between the local microprocessor (24) and memory (21). The arbiter (35) is implemented using a programmable logic device state machine approach, which implements a mode of operation wherein the circuitry is armed for a transfer between a local microprocessor (24) and the dual access memory (21) and accomplishes such transfer with no wait states. The state machines and dual access memory (21) are driven by a clock which is twice as fast as that driving the local microprocessor (24) and the state machine implementation utilizes this fact to insure memory access to both the system bus (13), and the local microprocessor (24) with priority going to the local microprocessor (24).

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