Internal address generator

Details Internal address generator Internal address generator

2008-05-27

2008-05-27

Nguyen, VanThu (Department: 2824)

Static information storage and retrieval

Addressing

Particular decoder or driver circuit

C365S230080, C365S233100

Reexamination Certificate

active

11478083

ABSTRACT:
An internal address generator includes a plurality of column address generators, a mode column address generator, and a drive clock generator. Each column generator receives a corresponding address, an additive latency, and a CAS latency to generate an internal read address in response to a read drive clock and generate an internal write address in response to a write drive clock. The mode column address generator receives a corresponding address, the additive latency, and the CAS latency to generate a mode read address in response to a band width read drive clock and generate a mode write address in response to a band width write drive clock. The drive clock generator receives an additive latency signal, a band width signal, a write enable signal, and a clock to generate the read drive clock, the write drive clock, the band width read drive clock, and the band width write drive clock.

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Korean Office Action issued in corresponding Korean Patent Application No. KR 2005-13396, dated Dec. 13, 2006.
Korean Office Action, issued in corresponding Korean Patent Application No. KR 10-2005-0133961, dated on Jun. 27, 2007.

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