Register file system for microcomputer including a decoding syst

Details Register file system for microcomputer including a decoding syst Register file system for microcomputer including a decoding syst

1995-05-03

1996-06-04

Chan, Eddie P.

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364DIG1, 3642602, 3649428, 3642543, 36523006, 395492, G06F 1202

Patent

active

055242260

ABSTRACT:
To speed up data transfer of a plurality of registers between register banks in a microcomptuer having a register file formed by a built-in RAM and consisting of a plurality of register banks, the memory cells of the same type of registers belonging to different register banks are connected to the same bit lines. For data transfer of a plurality of registers between register banks, the word line 12 connecting a source register bank is first activated to output data to bit lines 13, and then the word line 12 connecting to a destination register bank is activated to read the data outputted to the bit lines 13, thus making it possible to speed up data transfer of a plurality of registers without the use of the internal data bus 3 of the microcomputer.

REFERENCES:
patent: 4530108 (1985-07-01), Wilmsmeyer
patent: 4630195 (1986-12-01), Hester et al.
patent: 4879685 (1989-11-01), Takemae
patent: 5093783 (1992-03-01), Kitada
patent: 5177706 (1993-01-01), Shinohara
patent: 5197035 (1993-03-01), Ito
Introduction to VLSI System, Chapter 5, pp. 189, 195.

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