Fault-tolerant digital timing apparatus and method

Details Fault-tolerant digital timing apparatus and method Fault-tolerant digital timing apparatus and method

1987-02-25

1990-04-24

James, Andrew J.

Excavating

371 4, 371 471, 371 65, G06F 104, G06F 1120, H04Q 354

Patent

active

049205404

ABSTRACT:
Computer timing apparatus enables two clock elements to produce a single stream of timing pulses, without interruption, when both elements are operating normally, and when one element fails. The apparatus incorporates a multi-stable stage and an output logic stage. The multi-stable stage detects state transitions in the input signals of each clock element and generates a corresponding clock-tracking signal which can disable the output of the corresponding clock from propagating through the output logic. The output logic stage logically combines each clock signal with its corresponding clock-tracking signal, and logically combines the resultant signal to produce a single stream of output signals responsive to a next transition produced by either of the two clock elements.

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