Memory error correction system

Details Memory error correction system Memory error correction system

1988-06-20

1990-04-24

Fleming, Michael R.

Excavating

371 291, 371 13, G06F 1110

Patent

active

049205390

ABSTRACT:
A system for correcting soft memory failures such as alpha particle failures in a dynamic random access memory and in a computer system wherein writeback caches are employed in a system bus environment. The address field and source identification code associated with a detected data error are stored. A generic bus request signal is generated and upon a bus grant a read message is issued on the system bus having an address field and destination address code corresponding to the stored address field and source identification code. In response to the read message, the device indicated by the identification code writes back to memory the correct data corresponding to the address field.

REFERENCES:
patent: 4621364 (1986-11-01), Tshoepe
patent: 4646304 (1987-02-01), Fossati
patent: 4710934 (1987-12-01), Traynor
patent: 4791642 (1988-12-01), Taylor
patent: 4794597 (1988-12-01), Ooba
patent: 4800563 (1989-01-01), Itagati

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