Electrical pulse counters – pulse dividers – or shift registers: c – Systems – Counter controlled counter
Patent
1991-10-09
1992-08-25
Miller, Stanley D.
Electrical pulse counters, pulse dividers, or shift registers: c
Systems
Counter controlled counter
377 26, 377 55, G06F 900
Patent
active
051426510
ABSTRACT:
An uninterrupted event-time recorder enables high-precision measurements of the time-of-occurrence of randomly- and rapidly-occurring, digitally specified events such as the leading and/or trailing edges of asynchronous pulses. The lowest order binary digits of the recorder are constructed of high-speed synchronous integrated circuit counter devices. For an N-bit timer having M low-order bits, the highest order (N-M) bit counting is executed by two parallel (N-M)-bit slow-speed counters, one of which is incremented by the terminal count of the M-bit high-speed counter and the other which is incremented by the most significant bit (MSb) of the M-bit counter. The (N-M)-bit counters are read out through a multiplexer controlled by the MSb. The terminal count integrated counter is read out from the instant that the MSb goes high and until the MSb goes low (during which time the MSb-incremented counter is settling), while the MSb-incremented counter is read out from the instant that the MSb goes low up until the MSb goes high (during which time the terminal count incremented counter is settling). By utilizing this system real-time capture of event-time is possible with no delays associated with the settling of slow-speed counters. As such there are no cumulative clock count errors.
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Chu, David; "Phase Digitizing Sharpens Timing Measurements"; pp. 28-32; J 1988; New York, N.Y.
Fendelman Harvey
Keough Thomas G.
Lipovsky Peter A.
Miller Stanley D.
Ouellette Scott A.
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