System for employing select, pause, and identification registers

Details System for employing select, pause, and identification registers System for employing select, pause, and identification registers

1993-03-25

1996-06-04

Lee, Thomas C.

Boots, shoes, and leggings

395287, 395310, 364DIG1, 364280, 364230, 3642387, 3642445, G06F 1300, G06F 1516

Patent

active

055242111

ABSTRACT:
A control unit is assigned to each microprocessor of a multiprocessor (MP) system. Each control unit is in communication with its associated microprocessor and the system bus. Each control unit comprises a register set having bit registers and word registers. Messages can be sent to one or more of the microprocessors concurrently via a select function. Specifically, a data byte is bit sliced or bit masked so that the select register associated with one or more processors is activated. The bit registers which are activated, enable associated word registers for subsequent accesses. Consequently, one or more processors may be accessed concurrently. Moreover, bit pause registers are utilized so as to simultaneously pause one or more processors. Finally, bit identification registers may be read by any processor to determine the location of the processor.

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