Patent
1989-06-02
1992-08-25
James, Andrew J.
357 49, 357 59, H01L 2978, H01L 2712
Patent
active
051426404
ABSTRACT:
A trench gate MOS FET having one of the following features: a drain diffusion layer and/or a source diffusion layer having a two-layer structure consisting of a high concentration layer and a low concentration layer; at least a drain diffusion layer having a low concentration layer adjacent to the semiconductor surface of a trench gate and a high concentration layer adjacent to the low concentration layer; a gate oxide film formed to have a greater thickness at the overlapping portion of the diffusion layer and the gate electrode than at the other portions thereof; two trench gates provided on the semiconductor surface so as to control the conductivity of a channel region between the trench gates; or a trench isolation region provided on the semiconductor substrate in contact with the trench gate.
REFERENCES:
patent: 4486942 (1984-12-01), Hirao
patent: 4717941 (1988-01-01), Yamazaki
patent: 4721987 (1988-01-01), Baglee et al.
patent: 4774556 (1988-09-01), Fujii et al.
patent: 4794434 (1988-12-01), Pelley, III
patent: 4819054 (1989-04-01), Kawaji
patent: 4835586 (1989-05-01), Cogan et al.
James Andrew J.
Meier Stephen D.
Seiko Epson Corporation
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