Method for handling data between a clock and data recovery...

Multiplex communications – Pathfinding or routing – Combined circuit switching and packet switching

Reexamination Certificate

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Details

C370S395620, C370S395700, C370S514000, C370S516000, C375S371000, C375S372000, C710S029000, C714S022000

Reexamination Certificate

active

10720261

ABSTRACT:
A method for handling data between a clock and data recovery system CDR and a data processing unit DP of a telecommunications network node TNN of an asynchronous communications network, using a bit rate adaptation circuit BAS, the bit rate adaptation system BAS including a memory unit MEM with a write process circuit Wp controlled by the recovered clock Rclk and a read process circuit Rp controlled by the local clock Lclk where the bit rate adaptation system BAS also includes a pointer synchronization controller PSC which, depending on the data detected on the input data signal DIb1of the bit rate adaptation system BAS, sets the read and write pointers to a fixed initial address value. A Clock and Data Recovery system and a telecommunications network node TNN of an asynchronous network, which include a bit adaptation circuit BAS according to the invention, are also disclosed.

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